I/O List (DCS / SIS-IPS / F&G) — Final Self-Verification Checklist

Header & Document Control

• Document number/title follow project numbering; “I/O List (DCS/SIS/IPS/F&G)” clearly stated with unit/area/system.
• Revision index and purpose (IFR/IFA/IFC/IFD) correct; prepared/checked/approved names and dates completed.
• References listed with numbers & revisions (P&IDs, Loop/Interconnection, C&E Matrix, Alarm & Trip Schedule, SIF/IPF Register, F&G zoning, System Architecture, Client Specs).

Scope & Structure

• Scope includes all I/O channels for DCS/BPCS, SIS/IPS/ESD, and F&G, including package interfaces; exclusions clearly stated.
• Required columns present and consistently populated (Tag, Service, System, Loop No., Area/Unit, I/O Type (AI/AO/DI/DO/PI/PO), Signal Type, Card Type, Rack/Node, Slot, Channel, Scaling LRV/URV & Units, Filter/Scan, Alarms/Trips, Latch/Reset, SOE, Barriers/Isolators, Terminations (Panel/JB/Term), Cable ID, Power, Remarks/Refs).
• Unique channel key (System/Node–Slot–Channel) used; no duplicates; spares identified per policy with naming convention.

Tagging, Channels & Cross-References

• Instrument tags and descriptions match Instrument Index and P&IDs; loop numbers correct; device types per ISA-5.1/client legend.
• Channel allocations align with Panel/Rack layouts; marshalling terminal references correct; polarity and terminal numbering verified.
• Trips/causes reference C&E Matrix and SIF/IPF register where applicable; alarm rows reference Alarm & Trip Schedule codes.

Hardware & Card Specification

• Correct module type per signal (AI 4–20 mA/HART, RTD/TC, AO, DI Dry/NAMUR/24Vdc, DO Relay/Transistor, Pulse/Counter, FO Interface, F&G Loop).
• Card/channel isolation, accuracy, resolution, and diagnostic capability meet requirements; HART/FF pass-through where needed.
• Rack/node addresses, slot numbers, and channel numbering conform to vendor conventions; spare capacity tracked per rack.

Signal Conditioning, Barriers & Wiring

• Conditioners/isolation/barriers specified (e.g., AI isolator, galvanic isolator, Zener/Ex barrier) with model and location (panel/JB).
• Loop wiring references complete (cable ID, pair/triad mapping, shield bonding location, screen continuity); hook-up numbers included.
• Digital states and wetting defined (NO/NC, sourcing/sinking, NAMUR thresholds, debounce/delay on/off); fail-safe (E-to-trip/DE-to-trip) stated.

Scaling, Ranges & Units

• LRV/URV and Engineering Units populated; consistent with datasheets and process conditions; square-rooting location defined (TX vs DCS).
• Engineering range vs alarm/trip setpoints verified (margin from normal); linearization tables or characterizers referenced if used.
• Scan rate, filter/damping values appropriate to process dynamics; anti-chatter/averaging settings recorded where relevant.

Alarms, Trips & Digital States

• Alarm setpoints, priorities, classes/categories per Alarm Philosophy (EEMUA 191/ISA-18.2); texts concise (verb-object).
• Trip logic reference noted (C&E/SRS clause); latch/reset behavior stated; on/off delays entered; mode-based suppression documented.
• Bad PV/diagnostics mapping (NE 107) to alarm classes; out-of-range and saturation handling defined (clamp, substitute, alarm only).

Redundancy, Voting & Diagnostics

• Controller/rack/network redundancy captured where applicable; hot-standby/soft failover impacts on SOE/alarms considered.
• SIF sensors/final elements: voting (1oo2/2oo3/median) indicated; degradation rules on fault documented; PST hooks marked if relevant.
• Channel diagnostics (line fault detection, open/short, HART device alerts) enabled as required; annunciation path defined.

SOE, Time Sync & Timestamping

• SOE enabled for critical DI/logic points; timestamp source and resolution stated (e.g., 1 ms/10 ms); first-out requirements noted.
• Time synchronization method defined (NTP/PTP/IRIG); nodes/servers listed; loss-of-sync behavior documented.

Interfaces, Networks & System Assignment

• Hardwired vs serial/Ethernet interfaces identified (Modbus, OPC UA, Profibus/Profinet, FF, HART-IP); point mapping and ownership clear.
• Loss-of-comms behavior defined (hold last, trip, alarm); heartbeat/quality bits handled; integration node/rack identified.

Power, Earthing & Cabinet Details

• Channel supply/wetting documented (24 Vdc, source/sink, common returns); per-rack current loading within UPS/IPS capacity.
• Enclosure/panel IDs, ingress rating, ambient rating, and earthing/shielding philosophy recorded (single-point, marshalling, system).

Testing, FAT/SAT & Commissioning

• FAT/SAT/Loop check references present for each channel; simulation method (source, calibrator, jumpers) identified with acceptance criteria.
• Commissioning suppressions/inhibits listed with re-enable plan; MOC linkage established for temporary overrides.
• Data capture requirements (stroke/response time, calibration records, SOE validation) included where applicable.

Data Integrity & Formatting

• No duplicate channels or tags; mandatory fields complete; consistent units/decimal places; controlled use of “TBD”.
• Formulas/links in working file validated; hidden filters cleared; export/print area and page breaks set for issue.
• Revision history and change log updated with rationale and impacts; confidentiality/footer correct; transmittal list aligned.

Notes, Attachments & Final Polish

• Open items/assumptions listed with owners & dates; vendor data gaps highlighted; temporary settings flagged clearly.
• Attachments referenced with document numbers/revisions (architecture, marshalling layouts, panel layouts, vendor signal lists).
• Grammar/consistency check complete; abbreviations legend included; sample HMI/diagnostic screens if useful.
• Sanity scan: each channel traceable to a source within 60 seconds; conflicts with P&IDs/loops/Alarm & Trip/C&E resolved.