Loop Diagrams — Final Self-Verification Checklist

Header & Document Control

• Title states “Loop Diagram” with loop number, instrument tag(s), service, unit/area, and sheet X of Y; document number per project standard.
• Revision index & purpose (IFR/IFA/IFC/IFD) correct; prepared/checked/approved names and dates completed; change log maintained.
• References listed with numbers & revs (P&IDs, Instrument Datasheets, Instrument Index, I/O List, Interconnection/Termination, Hook-Ups, Cable & JB Schedule, C&E Matrix, Alarm & Trip Schedule, System Architecture, Client Standards).

Scope & Loop Structure

• Loop includes entire signal path: field device → cable → JB(s) → marshalling → system rack/slot/channel → controller/HMI/logic, with test points and spare cores shown.
• Loop members identified with correct ISA-5.1 function letters; loop number unique and consistent across all sheets and related documents.

Cross-References & Tagging

• Tags, descriptions, and loop numbers match Instrument Index & P&IDs; loop continuation arrows/callouts resolve to correct sheet numbers.
• I/O addresses (system/node, rack, slot, channel) match I/O List; card type and channel type (AI/AO/DI/DO/RTD/TC/pulse) correct.

Wiring, Cables & Terminations

• Cable IDs, cores/pairs/triads, wire numbers, and colors shown end-to-end; JB/panel IDs and terminal numbers correct; polarity clearly indicated.
• Shield/drain and armour bonding location stated (field/JB/system) per standard; jumpers/links/ferrules identified; spare cores landing/bonding shown.
• Entry glands/ratings (A1/A2, barrier, Ex d/e), IP/NEMA, and thread types referenced via Termination/Hook-Up drawings; unused entries plugged and labeled.

Analog Loops (4–20 mA / HART / FF)

• Loop-powered vs separately powered correctly shown; external resistors/characterizers indicated; HART mux/maintenance ports referenced if applicable.
• Isolators/barriers (Ex i/galvanic) shown with model/channel IDs; return/common wiring correct; analog output loading within limits; FF segment power/terminators/network IDs shown if FF.
• LRV/URV, ENG units, square-rooting location (TX vs DCS) and damping/filter notes present or referenced to I/O List; calibration/test points available.

Temperature & Pulse/Speed Loops

• RTD/TC wiring correct (3-wire/4-wire; TC polarity); CJC location and extension cable type noted; thermowell/lag info referenced to Hook-Up.
• Pulse/frequency devices (mag pickup/reed/open collector) show supply/wetting, debounce/Schmitt, counting direction, and isolation/barrier if needed.

Discrete, Solenoids, MOV/SDV & F&G

• DI logic and wetting shown (NO/NC, sourcing/sinking, NAMUR thresholds); debounce/ON-OFF delays indicated; SOE/first-out required points flagged.
• DO/solenoids include coil suppression (diode/RC), interposing relays if required, and fail-safe policy (E- or DE-to-trip) per philosophy; MOV wiring includes limit/torque, aux contacts, space heater, PST if applicable.
• F&G supervised loops show EOL resistor value/location; zone ID and voting/cause references included; sounders/beacons power paths identified.

Power, Earthing & Protection

• 24 Vdc (or other) supply shown with source/fuse/CB IDs; A/B redundancy and diode ORing where used; common returns clearly labeled and segregated if required.
• Earthing/bonding points shown; shield termination method consistent; hazardous area earthing/PA bonding per standard; surge protection devices indicated if specified.

Intrinsic Safety & Hazardous Areas

• Ex i barriers/isolators specified with model/channel IDs; segregation of IS vs non-IS terminals maintained; IS color coding/labels used where required.
• Entity parameters (Vmax/Imax/C/L) and cable parameters verified in loop calc; temperature class/EPL/IP ratings fit device and location.

Alarms, Trips & Logic References

• Alarm/trip setpoints and priorities referenced to Alarm & Trip Schedule; latch/reset and inhibit/suppression rules noted if loop-specific.
• C&E Matrix clause numbers/SIF IDs shown where loop participates in shutdowns or voting; safe state and action path indicated.

Graphics, Notes & CAD Quality

• Symbols/legends per client/ISA; signal flow arrows clear; text sizes/lineweights legible; no overlaps/clipped text; sheet index and continuation arrows tidy.
• Hyperlinks/callouts to related drawings valid (Termination, Interconnection, Hook-Up, Panel Layout, Vendor Diagram); PDFs export with selectable text; print areas/page breaks set.

Testing, Commissioning & Maintenance

• Loop check procedure references included (simulation points, expected readings, acceptance criteria); temporary jumpers/inhibits called out with re-enable plan.
• Calibration/bump test access feasible; PST/test solenoid and manual reset paths identified; SOE/time-stamp requirements captured for relevant points.

Data Integrity & Final Polish

• Consistency scan versus Instrument Index, I/O List, Cable/JB Schedule, Termination/Interconnection, Hook-Up, Alarm & Trip, and C&E; no duplicates/orphans.
• Mandatory fields complete; units/decimal places consistent; controlled use of “TBD”; revision history/transmittal and confidentiality/footer correct.

Notes, Attachments & Close-Out

• Open items/assumptions listed with owners & dates (e.g., vendor model confirmation, barrier selection, FF address plan); closure path defined.
• Attachments referenced with document numbers/revisions (vendor wiring, device manuals, segment drawings, calculations, 3D snapshots).